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NE56625-20 system reset with watchdog timer product data supersedes data of 2002 mar 25 2003 oct 15 integrated circuits
philips semiconductors product data NE56625-20 system reset with watchdog timer 2 2003 oct 15 general description the NE56625-20 is comprised of a power-on reset, a watchdog timer and low battery detection circuit. the ne56625 is designed to generate an active-low reset signal for a variety of microprocessor and logic systems. accurate reset signals are generated during momentary power interruptions or whenever power supply voltages sag to intolerable levels. the built-in watchdog timer monitors the microprocessor and ensures it is operating properly. any abnormal system operations due to microprocessor malfunctions are terminated by a system reset generated by the watchdog. to accommodate a wide range of system requirements, the watchdog monitoring time and power-on reset delay time are programmable from 10 ms to 10 sec. the NE56625-20 is designed for low voltage battery powered applications with low battery detection threshold at 2.2 v. it is offered in the 8-lead small outline surface mount package (sop005). features ? accurate threshold detection voltages: low battery: 2.2 v 3% power-on reset: 2.0 v 3% ? low hysteresis voltage (both low battery check and power-on reset): 50 mv typ. ? low supply current: 150 m a typ. ? programmable power-on reset detection voltage ? programmable power-on reset delay: 10 ms to 10 s ? internal watchdog timer programmable with external resistor and capacitor: 10 ms to 10 s ? reset assertion with v cc down to 0.8 v dc (typical) ? few external components required applications ? microcomputer systems and logic systems ? 2 v cordless phones ? various portable, battery operated equipment simplified system diagram 1 reset clk gnd c r ct v ref 8 3 v cc 6 NE56625-20 4 bc reset clk gnd r ct 2 nmi logic system battery check reset generator programmable watchdog timer c t 7 5 v s sl01593 figure 1. simplified system diagram.
philips semiconductors product data NE56625-20 system reset with watchdog timer 2003 oct 15 3 ordering information type number package temperature type number name description version range NE56625-20d so8 plastic small outline package; 8 leads; body width 3.9 mm sop005 20 to +75 c pin configuration sl01586 1 2 3 4 8 7 6 5 top view c t bc clk gnd reset v s r ct v cc NE56625-20 figure 2. pin configuration. pin description pin symbol description 1 c t t wdm , t wdr , t pr adjustment pin. t wdm , t wdr , t pr times are dependent on the value of external c t capacitor used. see figure 17 (timing diagram) for definition of t wdm , t wdr , t pr times. 2 bc battery check active-low output. 3 clk clock input pin from logic system for watchdog timer. 4 gnd circuit ground. 5 v cc positive supply voltage. 6 r ct watchdog timer control pin. the watchdog timer is enabled when this pin is pulled-up to v cc with a resistor, and disabled when this pin is connected to ground. 7 v s detection threshold adjustment pin. the detection threshold can be decreased by connecting this pin to v cc with a pull-up resistor. the detection threshold can be increased by connecting this pin to ground with a pull-down resistor. 8 reset reset active-low output. maximum ratings symbol parameter min. max. unit v cc power supply voltage 0.3 7 v v vs v s pin voltage 0.3 7 v v clk clk pin voltage 0.3 7 v v oh reset and bc pin voltage 0.3 7 v t oper operating temperature 20 +75 c t stg storage temperature 40 +125 c p power dissipation 300 mw
philips semiconductors product data NE56625-20 system reset with watchdog timer 2003 oct 15 4 recommended operating conditions symbol parameter rating unit v cc power supply voltage 1.9 to 6.5 v i olr reset sink current 0 to 500 m a i olc bc sink current 0 to 5.0 ma v ckh high-level clock input voltage < 1.0 v v ckl low-level clock input voltage < 0.2 v t wd clock monitoring time 1 to 10,000 ms t r(clk) , t f(clk) clock rise and fall times < 100 m s t r(vcc) power supply voltage rise time < 100 m s t f(vcc) power supply voltage fall time < 50 m s t amb operating ambient temperature 20 to +70 c c t tc capacitance 0.0022 to 2.2 m f dc electrical characteristics t amb = 25 c, v cc = 2.6 v, unless otherwise specified. symbol parameter conditions min. typ. max. unit i cc supply current during watchdog timer operation no load 0.7 1.0 ma v slr reset detection threshold v cc = falling; r ct : gnd; v s = open 1.94 2.0 2.06 v d v sr / d t amb temperature coefficient of reset detection voltage 20 c t amb 70 c 0.01 0.05 %/ c v hysr reset threshold hysteresis v cc = falling; r ct : gnd; v s = open 25 50 100 mv v slb battery detection voltage v cc = falling; r lb = 10 k w 2.13 2.20 2.27 v d v sb / d t amb temperature coefficient of battery detection voltage 0.01 0.05 %/ c v hysb battery hysteresis voltage v cc = falling; r lb = 10 k w 25 50 100 mv d v sl detection voltage difference d v sl = v slb v slr 175 200 225 mv v th clk input threshold 0.8 1.2 2.0 v i ih high-level clk input current v clk = 2.6 v 0 1 m a i il low-level clk input current v clk = 0 v 15 6 2 m a v ohr high-level output voltage, reset i reset = 1.0 m a; v s = open 2.0 2.2 v v ohb high-level output voltage, bc r lb = 10 k w 2.0 2.2 v v olr low-level output voltage, reset i reset = 500 m a; v cc = 1.8 v 0.3 0.5 v v olb low-level output voltage, bc i bc = 5 ma; v cc = 1.8 v 0.3 0.5 v i olr reset output sink current v reset = 0.5 v; v cc = 1.8 v 500 700 m a i olb battery check output sink current v bc = 0.5 v; v cc = 1.8 v 5 7 ma i ohr reset output source current v reset = 2.0 v 2 4 m a i ct1 c t charge current v ct = 0.5 v; during watchdog operation 0.3 0.15 0.075 m a i ct2 v ct = 0.5 v; during power-on reset operation 0.3 0.15 0.075 m a v ccl supply voltage to assert reset operation v reset = 0.4 v; i reset = 0.05 ma 0.8 1.0 v
philips semiconductors product data NE56625-20 system reset with watchdog timer 2003 oct 15 5 ac electrical characteristics characteristics measured with v cc = 2.6 v, and t amb = 25 c, unless otherwise specified. symbol parameter conditions min. typ. max. unit t p1 minimum power supply pulse width for detection 4.0 v negative-going v cc pulse 5.0 v 8.0 m s t clkw clock input pulse width 3.0 m s t clk clock input cycle 20 m s t wdm watchdog monitoring time (notes 1, 6) c t = 0.022 m f; r ct = open 50 100 150 ms t wdr watchdog reset time (notes 2, 6) c t = 0.022 m f 1.0 2.0 3.0 ms t pr power-on reset delay time (notes 3, 6) v cc = rising from 0 v; c t = 0.022 m f 50 100 150 ms t pdr reset propagation delay time (note 4) v cc = falling; r lr = 100 k w ; c lr = 15 pf 10 m s t pdb battery check propagation delay time (note 4) v cc = falling; r lb = 10 k w ; c lb = 15 pf 10 m s t rr reset rise time (note 5) r lr = 100 k w ; c lr = 15 pf 10 m s t fr reset fall time (note 5) r lr = 100 k w ; c lr = 15 pf 2 m s t rb battery check rise time (note 5) r lb = 10 k w ; c lb = 15 pf 10 m s t fb battery check fall time (note 5) r lb = 10 k w ; c lb = 15 pf 2 m s notes: 1. `watchdog monitoring time' (t wdm ) is the duration from the last pulse (negative-going edge) of the timer clear clock pulse until reset output pulse occurs (see figure 17). a reset signal is output if a clock pulse is not input during this time. 2. `watchdog reset time' (t wdr ) is the reset pulse width. do not confuse this with the power-on reset delay time (t pr ). 3. the power-on reset delay or hold time is the duration measured from the time v cc exceeds the upper detection threshold (v shr ) and power-on reset release is experienced (reset output high). 4. `reset response time' is the duration from when the supply voltage sags below the lower detection threshold (v sl ) and reset occurs (reset output low). 5. reset rise and fall times and battery check rise and fall times are measured at 10% and 90% output levels. 6. watchdog monitoring time (t wdm ), watchdog reset time (t wdr ), and power-on reset delay time (t pr ) during power-on can be modified by varying the c t capacitance. the times can be approximated by applying the following formula. the recommended range for c t is 0.0022 m f to 2.2 m f. formula 1. calculation for approximate t pr , t wdm , and t wdr values: t pr (ms) 4500 c t ( m f) t wdm (ms) 4500 c t ( m f) t wdr (ms) 90 c t ( m f) example: when c t = 0.022 m f and r ct = open: t pr 100 ms t wdm 100 ms t wdr 2.0 ms
philips semiconductors product data NE56625-20 system reset with watchdog timer 2003 oct 15 6 typical performance curves i cc , supply current ( a) m sl01818 ambient temperature, t amb ( c) 25 0 25 50 75 100 180 170 160 150 140 130 120 110 100 v cc = 2.4 v no load figure 3. supply current versus ambient temperature. low-level clk input current ( a) m sl01819 ambient temperature, t amb ( c) 25 0 25 50 75 100 2.95 3.00 3.05 3.10 3.15 3.20 3.25 v cc = 2.4 v v clk = 0 v figure 4. low-level clk input current versus ambient temperature. sl01820 supply voltage, v cc (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 5.0 3.5 4.0 4.5 6 5 4 3 2 1 0 battery detection voltage, v (v) slb v cc falling r lb = 10 k w t amb = 25 c t amb = +25 c t amb = +75 c t amb = +100 c figure 5. battery detection votlage versus supply voltage. sl01821 supply voltage, v cc (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 5.0 3.5 4.0 4.5 6 5 4 3 2 1 0 reset detection voltage, v (v) s v cc falling r lr = 100 k w r ct = gnd v s = open t amb = 25 c t amb = +25 c t amb = +75 c t amb = +100 c figure 6. reset detection voltage versus supply voltage. sl01822 supply voltage, v cc (v) 01 234 56 10 789 600 500 400 300 200 100 0 supply current, i ( a) cc t amb = 25 c t amb = +25 c t amb = +75 c t amb = +100 c m figure 7. supply current versus supply voltage. sl01823 high-level output current, i oh ( m a) 01 234 56 7 2.50 2.00 1.50 1.00 0.50 0.00 highlevel output voltage, v (v) oh t amb = 25 c t amb = +25 c t amb = +75 c t amb = +100 c i reset = 1 m a r lb = 10 k w v s = open figure 8. high-level output voltage versus high-level output current
philips semiconductors product data NE56625-20 system reset with watchdog timer 2003 oct 15 7 sl01824 battery check output sink current, i olb (ma) 02 4681012 20 14 16 18 1.2 1.0 0.8 0.6 0.4 0.2 0.0 t amb = 25 c t amb = +25 c t amb = +75 c t amb = +100 c low-level battery check output voltage v (v) olb i bc = 5 ma v bc = 0.5 v v cc = 2.0 v figure 9. battery check low-level output voltage versus battery check output sink current sl01825 reset output sink current, i olr (ma) 0.0 0.3 0.6 0.9 1.2 1.5 1.8 3.0 2.1 2.4 2.7 1.0 0.8 0.6 0.4 0.2 0.0 0.9 0.7 0.5 0.3 0.1 olr low-level reset output voltage, v (v) t amb = 25 c t amb = +25 c t amb = +75 c t amb = +100 c i reset = 500 m a v reset = 0.5 v v cc = 2.0 v v s = 0 v figure 10. low-level reset output voltage versus reset output sink current. sl01826 ambient temperature, t amb ( c) 25 0 25 50 75 100 2.35 2.30 2.25 2.20 2.15 2.10 2.05 reset and battery detection voltages v , v , v , v (v) slr slb shr shb 2.40 v shb v slb v shr v slr figure 11. reset and battery detection voltages versus temperature. sl01827 ambient temperature, t amb ( c) 25 0 25 50 75 100 140 120 100 80 60 40 20 reset and battery detection voltages v , v , v (v) sl hysr hysb 160 180 200 d v sl v hysr v hysb d figure 12. reset and battery hysteresis voltages versus temperature. sl01828 ambient temperature, t amb ( c) 25 0 25 50 75 100 100 80 60 40 20 power-on reset delay time, t (ms) pr v cc = 2.4 v c t = 0.022 m f v cc rising from 0 v to 2.4 v figure 13. power-on reset delay time versus temperature. sl01829 ambient temperature, t amb ( c) 25 0 25 50 75 100 90 85 80 75 70 65 60 watchdog monitoring time, t (ms) 95 wdm v cc = 2.4 v c t = 0.022 m f r ct = open figure 14. watchdog monitoring time versus temperature.
philips semiconductors product data NE56625-20 system reset with watchdog timer 2003 oct 15 8 sl01830 ambient temperature, t amb ( c) 25 0 25 50 75 100 1.6 1.5 1.4 1.3 1.2 1.1 1.0 watchdog reset delay time, t (ms) 1.7 1.8 1.9 wdr 2.0 v cc = 2.4 v c t = 0.022 m f figure 15. watchdog reset delay time versus temperature.
philips semiconductors product data NE56625-20 system reset with watchdog timer 2003 oct 15 9 technical description the NE56625-20 combines a watchdog timer, a battery check and an undervoltage reset functions in a single so8 surface mount package. this provides a space-saving solution for maintaining proper operation of typical 2.0 volt cordless telephone and other low voltage portable, handheld communication and industrial equipment. while the watchdog monitors the microprocessor operation, the battery check and undervoltage reset monitor the supply voltage to the microprocessor. if the microprocessor clock signal ceases or becomes erratic, the NE56625-20 outputs a reset signal to the microprocessor. if the microprocessor supply voltage sags to 2.0 volts or less, the NE56625-20 outputs a reset signal for the duration of the supply voltage deficiency. the undervoltage reset signal allows the microprocessor to shut down in an orderly manner to avoid system corruption. in addition to a reset output, the NE56625-20 has a battery check output for system use. if the supply voltage sags below 2.2 volts or less, the battery check output goes low and remains low until the supply voltage recovers. both the undervoltage detection threshold and battery check detection threshold incorporate hysteresis to prevent generating erratic resets. the watchdog timer requires a pulse input. normally this signal comes from the system microprocessor's clock. for operation, pin 6 is not connected (open) or an external resistor (r ct ) of 1 m w or greater is connected from pin 6 to v cc and an external capacitor (c t ) is placed from pin 1 to ground. the recommended range for c t capacitor is 2.2 nf to 2.2 m f. the external r ct resistor and c t capacitor establish the required minimum frequency of watchdog input signal for the device to not output a reset signal. the r ct resistor establishes, in part, the rate of charge of the c t capacitor. in the absence of a watchdog input pulse, the c t capacitor charges to the 0.2 volt threshold of the internal comparator, causing a reset signal to be output. if microprocessor clock signals are received within the required interval, no watchdog reset signal will be output. the watchdog function can be disabled by grounding pin 6 without affecting the undervoltage detection function. although the temperature coefficient of detection threshold is specified over a temperature of 20 c to +70 c, the device will support operation in excess of this temperature range. see the supporting curves for performance over the full temperature range of 25 c to +100 c. some degradation in performance will be experienced at the temperature extremes and the system designer should take this into account. sl01594 8 4 3 s q 7 q reset 1 c t 6 gnd r ct pulse generator 1 m a (typ.) 0.1 v 0.2 v 230 k w 250 k w c v cc s r q s r r 0.15 a (typ) m 2 bc 1.25 v (typ.) clk v s r ct 5 c v cc figure 16. functional diagram.
philips semiconductors product data NE56625-20 system reset with watchdog timer 2003 oct 15 10 timing diagram the timing diagram shown in figure 17 depicts the operation of the device. letters indicate events on the time axis. a: at start-up `a', the v cc voltage begins to rise. also the reset and battery check (bc) voltages initially rise, but then abruptly return to a low state. this is due to v cc reaching the level of 0.8 v that activates the internal bias circuitry, asserting reset and bc. b: just before `b', the c t voltage starts to ramp up. this is caused by, and coincident to, v cc reaching the threshold level of v shr . at this level the device initiates the reset delay time, t plh . v cc continues to rise above v shr . c: at `c', v cc rises to the threshold level of v shb , the upper voltage bc detection threshold. at this level, the bc output goes high. bc output follows v cc to its normal operating level. d: at `d', v cc is above the undervoltage detect threshold and c t has ramped up to its upper detect level. at this point, an internal ramp discharge transistor activates, discharging c t . reset assertion is still in effect since the delay time has not elapsed. e: at `e', the delay time has elapsed and the device removes the hold on the reset. reset goes high. in a microprocessor based system these events remove the reset from the microprocessor, allowing it to function normally. the system must send clock signals to the watchdog timer often enough to prevent c t from ramping up to the c t threshold, to prevent reset signals from being generated. each clock signal discharges c t . ef: midway between `e' and `f', the clk signals cease allowing the c t voltage to ramp up to its reset threshold at `f'. at this time reset signals are generated (reset goes low). the device attempts to come out of reset as the c t voltage is discharged, and finally does come out of reset when clk signals are reestablished after two attempts of c t . gi: immediately before `g', falling v cc causes the reset and bc outputs to sag. clk signals are still being received, and c t is within normal operating range. v cc continues to sag until the v slb battery check undervoltage threshold is reached. at that time (g), bc output goes low. v cc sags still further until v slr reset undervoltage threshold is reached. at this point (h), reset is asserted and reset goes low. between `h' and `i', v cc starts to rise, however, c t voltage does not start to ramp up until `i', when v cc reaches the v shr upper reset threshold. also, the reset delay is initiated. jk: at `j', the bc output goes high when v cc rises to v shb . between `j' and `k, c t reaches the upper threshold level again. at `k', reset delay time elapses and the reset is released and reset goes high. lm: from `l' to `m', the r ct is shorted to ground. this disables the watchdog timer by shorting c t to ground. at other times r ct is open or taken to v cc with a resistor of 1 m w or greater. this configuration enables the watchdog timer. n: after `n', normal clk signals are received, but at a lower frequency than those following event `d'. the frequency is above the minimum frequency required to keep the device from outputting reset signals. op: at `o', v cc is normal, clk signals are being received, and no reset signals are output. at event `p', the v cc starts falling, causing reset and bc to also fall. q: at event `q' v cc sags to the point where the v slr undervoltage threshold point is reached, and at that level reset signal is outputted (reset to a low state). r: at event `r' the v cc voltage has deteriorated to a level where normal internal circuit bias is no longer able to maintain a reset , and as a result may exhibit a slight rise to something less than 0.8 v. as v cc decays even further, reset also decreases to zero.
philips semiconductors product data NE56625-20 system reset with watchdog timer 2003 oct 15 11 v shb v slb v shr v slr 0.8 v v cc clk c t reset bc open abc de f ghij k l m no pqr r ct t clkw t clk t wdm t wdr t pr sl01592 figure 17. timing diagram.
philips semiconductors product data NE56625-20 system reset with watchdog timer 2003 oct 15 12 application information detection threshold the detection threshold voltage can be adjusted by externally influencing the internal divider reference voltage. figures 18 and 20 show a method to raise and lower the threshold voltage. figures 19 and 21 show the influence of the pull-down and pull-up resistors on the threshold voltage. the use of a capacitor (1000 pf or larger) from pin 7 to ground is recommended to filter out noise from being imposed on the threshold voltages. the reset detection threshold can be increased by connecting an external resistor r 1 from pin 7 to ground, as shown in figure 18. see figure 19 to determine the approximate value of r 1 to use. the threshold made be varied somewhat linearly from 2.4 v to 3.0 v. the reset detection threshold can be decreased by connecting an external resistor r 2 from pin 7 to v cc , as shown in figure 20. see figure 21 to determine the approximate value of r 2 to use. the lower thresholds may be varied in a linear fashion from 1.85 v to 1.65 v. sl01588 1 2 3 4 8 7 6 5 reset nmi clk gnd logic system 1000 pf NE56625-20 v cc c t r 2 figure 18. circuit to raise detection threshold. sl01590 3.1 3.0 2.9 2.8 2.7 2.6 2.5 2.4 2.3 t amb = 25 c 200 300 400 500 600 700 800 900 r 1 , external pin 7 to ground resistor (k w ) vs, reset detection threshold (v) v shr v slr figure 19. reset detection threshold versus external r 1 . sl01589 1 2 3 4 8 7 6 5 reset nmi clk gnd logic system 1000 pf NE56625-20 v cc c t r 1 figure 20. circuit to lower detection threshold. sl01591 1.9 1.8 1.7 1.6 200 300 400 500 600 700 800 900 r 2 , external pin 7 to v cc resistor (k w ) vs, reset detection threshold (v) t amb = 25 c v shr v slr figure 21. reset detection threshold versus external r 2 .
philips semiconductors product data NE56625-20 system reset with watchdog timer 2003 oct 15 13 watchdog monitoring time the watchdog timer's external component values are critical to its performance. the values of r ct and c t affect the watchdog monitoring time (t wdm ), the watchdog reset time (t wdr ), and power-on reset delay time (t pr ). see formula 1 in the ac electrical characteristics and the timing diagram shown in figure 17 for parameter definitions. the effect of r ct on the watch-dog timer monitoring time at room temperature for c t = 0.0022 m f is shown in figure 22. sl01587 10k 100k 1m 10m 100m 0 20 40 60 80 100 c t = 0.0022 m f t amb = 25 c r ct , watchdog timer current resistor ( w ) t wdm , watchdog monitor time (ms) figure 22. watchdog monitoring vs. pull-up resistor r ct . packing method the NE56625-20 is packed in reels, as shown in figure 23. sl01305 tape detail cover tape carrier tape reel assembly tape guard band barcode label box figure 23. tape and reel packing method.
philips semiconductors product data NE56625-20 system reset with watchdog timer 2003 oct 15 14 so8: plastic small outline package; 8 leads; body width 3.9 mm sop005
philips semiconductors product data NE56625-20 system reset with watchdog timer 2003 oct 15 15 revision history rev date description _2 20031015 product data (9397 750 12124). ecn 853-2327 30314 of 08 september 2003. supersedes data of 2002 mar 25 (9397 750 09645). modifications: ? change package version to sop005 in ordering information and package outline sections. _1 20020325 product data (9397 750 09645). ecn 853-2327 27919 of 25 march 2002. definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed i nformation see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the l imiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any o ther conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affec t device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors ma ke no representation or warranty that such applications will be suitable for the specified use without further testing or modificatio n. disclaimers life support e these products are not designed for use in life support appliances, devices, or systems where malfunction of these products ca n reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applica tions do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes in the productseincluding circuits, standard cells, and/or softwaree described or contained herein in order to improve design and/or performance. when the product is in full production (status `production') , relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for th e use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranti es that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2003 all rights reserved. printed in u.s.a. date of release: 10-03 document order number: 9397 750 12124

data sheet status [1] objective data preliminary data product data product status [2] [3] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change notification (cpcn). data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level i ii iii

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